Phase-locked loops are generally used in digital systems requiring a significant internal working frequency, for example of the order of several hundred megahertz.
The role of phase-locked loops is therefore in particular to deliver to these digital systems, for example a programmable core or a microprocessor, an internal clock signal having a significant working frequency.
Disturbances such as for example electromagnetic and/or electrostatic disturbances can arise on startup and/or during the operation of the phase-locked loop.
These disturbances are all the more troublesome as they can lead to the absence of the feedback signal arising from the output signal of the oscillator of the phase-locked loop and intended for the loop's phase comparator.
The phase-locked loop is then considered to be in an off state.
In order to turn the phase-locked loop back on and thus receive the feedback signal arising from the output signal of the oscillator of the phase-locked loop, it is known to undertake a complete reinitialization of the system, in particular of the microprocessor, this not constituting a satisfactory solution.